libgambatte: simplify a bit
parent
cca5f5a5bf
commit
cfdc505f23
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@ -1194,7 +1194,7 @@ void gambatte::setInitState(SaveState &state, bool const cgb, bool const gbaCgbM
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setInitialDmgIoamhram(state.mem.ioamhram.ptr);
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}
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state.mem.ioamhram.ptr[0x104] = 0x1C;
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state.mem.ioamhram.ptr[0x104] = 0x00;
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state.mem.ioamhram.ptr[0x140] = 0x91;
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state.mem.ioamhram.ptr[0x144] = 0x00;
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@ -1202,7 +1202,7 @@ void gambatte::setInitState(SaveState &state, bool const cgb, bool const gbaCgbM
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// This also applies to the TIMA and PSG frame sequencer, which may suggest
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// that div reset could affect the other two.
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// TODO: test whether div reset can affect other counters.
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state.mem.divLastUpdate = 0;
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state.mem.divLastUpdate = -0x1C00;
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state.mem.timaLastUpdate = 0;
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state.mem.tmatime = disabled_time;
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state.mem.nextSerialtime = disabled_time;
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@ -1221,7 +1221,6 @@ void gambatte::setInitState(SaveState &state, bool const cgb, bool const gbaCgbM
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state.mem.rambankMode = false;
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state.mem.hdmaTransfer = false;
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for (int i = 0x00; i < 0x40; i += 0x02) {
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state.ppu.bgpData.ptr[i ] = 0xFF;
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state.ppu.bgpData.ptr[i + 1] = 0x7F;
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@ -67,6 +67,7 @@ void Memory::setStatePtrs(SaveState &state) {
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unsigned long Memory::saveState(SaveState &state, unsigned long cc) {
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cc = resetCounters(cc);
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ioamhram_[0x104] = 0;
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nontrivial_ff_read(0x05, cc);
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nontrivial_ff_read(0x0F, cc);
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nontrivial_ff_read(0x26, cc);
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@ -96,7 +97,7 @@ void Memory::loadState(SaveState const &state) {
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cart_.loadState(state);
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intreq_.loadState(state);
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divLastUpdate_ = state.mem.divLastUpdate;
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divLastUpdate_ = state.mem.divLastUpdate - 0x100l * state.mem.ioamhram.get()[0x104];
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intreq_.setEventTime<intevent_serial>(state.mem.nextSerialtime > state.cpu.cycleCounter
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? state.mem.nextSerialtime
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: state.cpu.cycleCounter);
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@ -456,16 +457,9 @@ unsigned long Memory::resetCounters(unsigned long cc) {
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updateIrqs(cc);
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{
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unsigned long divinc = (cc - divLastUpdate_) >> 8;
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ioamhram_[0x104] = (ioamhram_[0x104] + divinc) & 0xFF;
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divLastUpdate_ += divinc << 8;
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}
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unsigned long const dec = cc < 0x10000
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unsigned long const dec = cc < 0x20000
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? 0
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: (cc & ~0x7FFFul) - 0x8000;
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decCycles(divLastUpdate_, dec);
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: (cc & -0x10000l) - 0x10000;
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decCycles(lastOamDmaUpdate_, dec);
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decEventCycles(intevent_serial, dec);
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decEventCycles(intevent_oam, dec);
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@ -574,13 +568,7 @@ unsigned Memory::nontrivial_ff_read(unsigned const p, unsigned long const cc) {
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updateSerial(cc);
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break;
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case 0x04:
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{
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unsigned long divcycles = (cc - divLastUpdate_) >> 8;
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ioamhram_[0x104] = (ioamhram_[0x104] + divcycles) & 0xFF;
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divLastUpdate_ += divcycles << 8;
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}
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break;
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return (cc - divLastUpdate_) >> 8 & 0xFF;
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case 0x05:
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ioamhram_[0x105] = tima_.tima(cc);
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break;
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@ -705,7 +693,6 @@ void Memory::nontrivial_ff_write(unsigned const p, unsigned data, unsigned long
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data |= 0x7E - isCgb() * 2;
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break;
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case 0x04:
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ioamhram_[0x104] = 0;
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divLastUpdate_ = cc;
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return;
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case 0x05:
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@ -19,9 +19,13 @@
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#include "tima.h"
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#include "savestate.h"
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static unsigned char const timaClock[4] = { 10, 4, 6, 8 };
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using namespace gambatte;
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namespace gambatte {
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namespace {
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unsigned char const timaClock[] = { 10, 4, 6, 8 };
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}
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Tima::Tima()
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: lastUpdate_(0)
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@ -47,8 +51,8 @@ void Tima::loadState(SaveState const &state, TimaInterruptRequester timaIrq) {
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unsigned long nextIrqEventTime = disabled_time;
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if (tac_ & 4) {
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nextIrqEventTime = tmatime_ != disabled_time && tmatime_ > state.cpu.cycleCounter
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? tmatime_
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: lastUpdate_ + ((256u - tima_) << timaClock[tac_ & 3]) + 3;
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? tmatime_
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: lastUpdate_ + ((256u - tima_) << timaClock[tac_ & 3]) + 3;
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}
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timaIrq.setNextIrqEventTime(nextIrqEventTime);
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@ -128,13 +132,10 @@ void Tima::setTac(unsigned const data, unsigned long const cc, TimaInterruptRequ
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if (tac_ & 0x04) {
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updateIrq(cc, timaIrq);
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updateTima(cc);
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// FIXME: this looks naive.
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// TODO: more TIMA tests.
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lastUpdate_ -= (1u << (timaClock[tac_ & 3] - 1)) + 3;
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tmatime_ -= (1u << (timaClock[tac_ & 3] - 1)) + 3;
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nextIrqEventTime -= (1u << (timaClock[tac_ & 3] - 1)) + 3;
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if (cc >= nextIrqEventTime)
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timaIrq.flagIrq();
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@ -167,5 +168,3 @@ void Tima::doIrqEvent(TimaInterruptRequester timaIrq) {
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timaIrq.setNextIrqEventTime(timaIrq.nextIrqEventTime()
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+ ((256u - tma_) << timaClock[tac_ & 3]));
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}
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}
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